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Imai, Shigeru, Kato, Hiroki, Hiraoka, Yasuhiro (2012) Stability Diagrams of Single-Common-Gate Double-Dot Single-Electron Transistors with Arbitrary Junction and Gate Capacitances. Japanese Journal of Applied Physics, 51 (12) 124301 doi:10.7567/jjap.51.124301

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Reference TypeJournal (article/letter/editorial)
TitleStability Diagrams of Single-Common-Gate Double-Dot Single-Electron Transistors with Arbitrary Junction and Gate Capacitances
JournalJapanese Journal of Applied Physics
AuthorsImai, ShigeruAuthor
Kato, HirokiAuthor
Hiraoka, YasuhiroAuthor
Year2012 (December 1)Volume51
Issue12
PublisherJapan Society of Applied Physics
DOIdoi:10.7567/jjap.51.124301Search in ResearchGate
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Mindat Ref. ID15042008Long-form Identifiermindat:1:5:15042008:0
GUID0
Full ReferenceImai, Shigeru, Kato, Hiroki, Hiraoka, Yasuhiro (2012) Stability Diagrams of Single-Common-Gate Double-Dot Single-Electron Transistors with Arbitrary Junction and Gate Capacitances. Japanese Journal of Applied Physics, 51 (12) 124301 doi:10.7567/jjap.51.124301
Plain TextImai, Shigeru, Kato, Hiroki, Hiraoka, Yasuhiro (2012) Stability Diagrams of Single-Common-Gate Double-Dot Single-Electron Transistors with Arbitrary Junction and Gate Capacitances. Japanese Journal of Applied Physics, 51 (12) 124301 doi:10.7567/jjap.51.124301
In(2012, December) Japanese Journal of Applied Physics Vol. 51 (12) Japan Society of Applied Physics


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