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Mizuno, Tomohisa, Moriyama, Yoshihiko, Tezuka, Tsutomu, Sugiyama, Naoharu, Takagi, Shin-ichi (2011) Single Source Heterojunction Metal–Oxide–Semiconductor Transistors for Quasi-Ballistic Devices: Optimization of Source Heterostructures and Electron Velocity Characteristics at Low Temperature. Japanese Journal of Applied Physics, 50 (1) 10107 doi:10.7567/jjap.50.010107

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Reference TypeJournal (article/letter/editorial)
TitleSingle Source Heterojunction Metal–Oxide–Semiconductor Transistors for Quasi-Ballistic Devices: Optimization of Source Heterostructures and Electron Velocity Characteristics at Low Temperature
JournalJapanese Journal of Applied Physics
AuthorsMizuno, TomohisaAuthor
Moriyama, YoshihikoAuthor
Tezuka, TsutomuAuthor
Sugiyama, NaoharuAuthor
Takagi, Shin-ichiAuthor
Year2011 (January 1)Volume50
Issue1
PublisherJapan Society of Applied Physics
DOIdoi:10.7567/jjap.50.010107Search in ResearchGate
Generate Citation Formats
Mindat Ref. ID15036725Long-form Identifiermindat:1:5:15036725:5
GUID0
Full ReferenceMizuno, Tomohisa, Moriyama, Yoshihiko, Tezuka, Tsutomu, Sugiyama, Naoharu, Takagi, Shin-ichi (2011) Single Source Heterojunction Metal–Oxide–Semiconductor Transistors for Quasi-Ballistic Devices: Optimization of Source Heterostructures and Electron Velocity Characteristics at Low Temperature. Japanese Journal of Applied Physics, 50 (1) 10107 doi:10.7567/jjap.50.010107
Plain TextMizuno, Tomohisa, Moriyama, Yoshihiko, Tezuka, Tsutomu, Sugiyama, Naoharu, Takagi, Shin-ichi (2011) Single Source Heterojunction Metal–Oxide–Semiconductor Transistors for Quasi-Ballistic Devices: Optimization of Source Heterostructures and Electron Velocity Characteristics at Low Temperature. Japanese Journal of Applied Physics, 50 (1) 10107 doi:10.7567/jjap.50.010107
In(2011, January) Japanese Journal of Applied Physics Vol. 50 (1) Japan Society of Applied Physics

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Mizuno, Tomohisa, Moriyama, Yoshihiko, Tezuka, Tsutomu, Sugiyama, Naoharu, Takagi, Shin-ichi (2011) Single Source Heterojunction Metal–Oxide–Semiconductor Transistors for Quasi-Ballistic Devices: Optimization of Source Heterostructures and Electron Velocity Characteristics at Low Temperature. Japanese Journal of Applied Physics, 50. 10107 doi:10.1143/jjap.50.010107
Sugiyama, Naoharu, Moriyama, Yoshihiko, Tezuka, Tsutomu, Mizuno, Tomohisa, Nakaharai, Shu, Usuda, Koji, Takagi, Sin-ichi (2003) Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method. Japanese Journal of Applied Physics, 42. 4476-4479 doi:10.1143/jjap.42.4476
Mizuno, Tomohisa, Mizoguchi, Naoki, Tanimoto, Kotaro, Yamauchi, Tomoaki, Hasegawa, Mitsuo, Sameshima, Toshiyuki, Tezuka, Tsutomu (2010) New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices. Japanese Journal of Applied Physics, 49 (4) 4 doi:10.1143/jjap.49.04dc13
Usuda, Koji, Mizuno, Tomohisa, Tezuka, Tsutomu, Sugiyama, Naoharu, Moriyama, Yoshihiko, Nakaharai, Shu, Takagi, Shin-ichi (2004) Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation. Applied Surface Science, 224. 113-116 doi:10.1016/j.apsusc.2003.11.058
Takagi, Shin-ichi, Mizuno, Tomohisa, Tezuka, Tsutomu, Sugiyama, Naoharu, Numata, Toshinori, Usuda, Koji, Moriyama, Yoshihiko, Nakaharai, Shu, Koga, Junji, Tanabe, Akihito, Maeda, Tatsuro (2004) Fabrication and device characteristics of strained-Si-on-insulator (strained-SOI) CMOS. Applied Surface Science, 224. 241-247 doi:10.1016/j.apsusc.2003.08.070
Mizuno, Tomohisa, Hasegawa, Mitsuo, Ikeda, Keiji, Nojiri, Masashi, Horikawa, Tsuyoshi (2011) Abrupt Lateral-Source Heterostructures with Relaxed/Strained Layers for Ballistic Complementary Metal Oxide Semiconductor Transistors Fabricated by Local O+Ion-Induced Relaxation Technique of Strained Substrates. Japanese Journal of Applied Physics, 50 (4) 4 doi:10.7567/jjap.50.04dc02
Mizuno, Tomohisa, Sugiyama, Naoharu, Tezuka, Tsutomu, Takagi, Shin-ichi (2002) Relaxed SiGe-on-insulator substrates without thick SiGe buffer layers. Applied Physics Letters, 80 (4). 601-603 doi:10.1063/1.1435799
Tezuka, Tsutomu, Sugiyama, Naoharu, Mizuno, Tomohisa, Suzuki, Masamichi, Takagi, Shin-ichi (2001) A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs. Japanese Journal of Applied Physics, 40. 2866-2874 doi:10.1143/jjap.40.2866
Mizuno, Tomohisa, Hasegawa, Mitsuo, Ikeda, Keiji, Nojiri, Masashi, Horikawa, Tsuyoshi (2011) Abrupt Lateral-Source Heterostructures with Relaxed/Strained Layers for Ballistic Complementary Metal Oxide Semiconductor Transistors Fabricated by Local O+Ion-Induced Relaxation Technique of Strained Substrates. Japanese Journal of Applied Physics, 50 (4) 4 doi:10.1143/jjap.50.04dc02
Nakaharai, Shu, Tezuka, Tsutomu, Sugiyama, Naoharu, Moriyama, Yoshihiko, Takagi, Shin-ichi (2003) Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique. Applied Physics Letters, 83 (17). 3516-3518 doi:10.1063/1.1622442
Tezuka, Tsutomu, Hirashita, Norio, Moriyama, Yoshihiko, Sugiyama, Naoharu, Usuda, Koji, Toyoda, Eiji, Murayama, Ken, Takagi, Shin-ichi (2008) {110}-facets formation by hydrogen thermal etching on sidewalls of Si and strained-Si fin structures. Applied Physics Letters, 92 (19). 191903pp. doi:10.1063/1.2924281
 
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